Today's integrated circuits include a vast number of devices housed in a semiconductor. Smaller devices are the key to enhance performance and to increase reliability. As devices are scaled down, however, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next. In this regard the semiconductor that has progressed the farthest is the primary semiconducting material of microelectronics, silicon (Si), or more broadly, to Si based materials. Such a Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy.
One of the most important indicators of potential device performance is the carrier mobility. There is great difficulty in keeping carrier mobility high in devices of deeply submicron generations. A promising avenue toward better carrier mobility is to modify slightly the semiconductor that serves as raw material for device fabrication. It has been known, and recently further studied, that tensilely or compressively straining semiconductors have intriguing carrier properties. A Si layer embedded in a Si/SiGe heterostructure grown by UHV-CVD has demonstrated enhanced transport properties, namely carrier mobilities, over bulk Si. In particular, a 90-95% improvement in the electron mobility has been achieved in a strained Si channel NMOS in comparison to a bulk Si NMOS mobility. (NMOS stand for N-channel Metal Oxide Semiconductor transistor, a name with historic connotations for Si Field-Effect-Transistors (FET). PMOS stands for P-channel Metal Oxide Semiconductor transistor).
Germanium (Ge) has attractive hole carrier properties. It is for this reason that the SiGe alloy is an advantageous material for hole conduction type devices. The band structures of Si and Ge, and of the SiGe alloy, as well, are such that the hole transport, primarily hole mobility, improves if the materials are under compressive strain.
Ideally, one would like to have integrated circuit such that the electron conduction type devices, such as NMOS, NMODFET are hosted in a strained Si or SiGe material, while the hole conduction type devices, such as PMOS, PMODFET are hosted in a compressed Ge or SiGe material. NMODFET stands of N-Modulation Doped FET. (PMOS and PMODFET stand for the corresponding P type devices.) The term of hosting a device in a certain material, or layer, means that the critical part of the device, that which is mainly sensitive to carrier properties, such as, for instance, the channel of MOS devices, is residing in, composed of, housed in, that certain material, or layer.
The great difficulty lies in producing materials of tensilely strained Si, or SiGe, together with compressively strained SiGe, or Ge, that are of high enough crystalline quality, namely practically free of dislocations and other defects, that can satisfy the exceeding demands of microelectronics applications. Such crystalline material quality is usually referred to as microelectronics quality. For defects, microelectronics quality means a density below about 105/cm2. Fabricating tensilely or compressively strained microelectronics quality SiGe layers by themselves is exceedingly difficult, but having them side by side in the same crystalline layer, ready to host the respective devices adds even more complications.
If one achieves a materials of sufficiently good quality, with high carrier mobilities in the of form thin layers, the underlying substrate may be a source of defects that eventually find their way into the good quality material on the surface as a result of device fabrication or integration. An additional potential area of concern is the interaction of a semiconducting substrate with active devices on the surface. The underlying semiconducting substrate may introduce features which could limit the harvesting of the full advantage that a superior strained device layer can bestow. Often today's state of the art devices operate in a semiconducting layer which is separated from the semiconducting substrate by an insulating layer. This technology is commonly knows as SOI technology. (SOI stands for Si-on-insulator.) The standard method of producing SOI materials is called the SIMOX process. It involves the implantation of very high doses of oxygen ions at high energy into the semiconductor, and upon annealing, the oxygen forms an oxide layer under the surface of the semiconductor. In this manner one has a top semiconductor layer separated from the bulk of the substrate. However, the SIMOX process has many of its own problems that makes it unsuitable for the production of high mobility strained layers.